Open-source Simulators
| Simulator Name | Author/Company | Supported Languages | Description |
|---|---|---|---|
| GPL Cver | Pragmatic C Software | V1995, minimal V2001 | This is a GPL open-source simulator. It is a pure simulator. This simulator is not fully IEEE 1364-2001 compliant. It does not support generate and constant functions. |
| Icarus Verilog | Stephen Williams | V1995, V2001, limited V2005/V2009 | Also known as iverilog; this simulator is not fully IEEE 1364-2001 compliant as it does not support constant functions, parameterized functions. Generate statements are now supported. |
| Verilator | Veripool | Synthesizable V2001, synthesizable V2005, minimal synthesizable SV2009 | This is a very high speed open-source simulator that compiles synthesizable Verilog to C++/SystemC. |
| VeriWell | Elliot Mednick | V1995 | This simulator used to be commercial, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364-1995. |
| LIFTING | A. Bosio, G. Di Natale (LIRMM) | V1995 | LIFTING (LIRMM Fault Simulator) is an open-source simulator able to perform both logic and fault simulation for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. |
Read more about this topic: List Of Verilog Simulators