Interrupts in 65xx Processors - WAI and STP Instructions

WAI and STP Instructions

WAI (WAit for Interrupt) is an instruction (opcode $CB) available on the WDC version of the 65C02 and the 65C816/65C802 microprocessors (MPU) that halts the MPU and places it into a semi-catatonic state until a hardware interrupt of any kind occurs. The primary use for WAI is in low-power embedded systems where the MPU has nothing to do until an expected event occurs, minimal power consumption is desired as the system is waiting and a quick response is required. A typical example of code that would make use of WAI is as follows:

In the above code fragment, the MPU will halt upon execution of WAI and go into a very low power consumption state. Despite interrupt requests (IRQ) having been disabled prior to the WAI instruction, the MPU will respond to any hardware interrupt while waiting. Upon receipt of an interrupt, the MPU will "awaken" in one clock cycle and resume execution at the instruction immediately following WAI. Hence interrupt latency will be very short (70 nanoseconds at 14 megahertz), resulting in the most rapid response possible to an external event.

Similar in some ways to WAI is the STP (SToP) instruction (opcode $DB), which completely shuts down the MPU while waiting for a single interrupt input. When STP is executed, the MPU halts its internal clock (but does retain all data in its registers) and enters a low power state. The MPU is brought out of this state by pulling its reset input pin (RESB, which is classified as an interrupt input) low. Execution will then resume at the address stored at locations $00FFFC-$00FFFD, the hardware reset vector. As with WAI, STP is intended for use in low power embedded applications where long periods of time may elapse between events that require MPU attention and no other processing is required. STP would not be used in normal programming, as it would result in total cessation of processing.