Interrupts in 65xx Processors - ABORT Interrupt

ABORT Interrupt

The 65C816's ABORT input is intended to provide the means to interrupt the processor when a hardware exception is detected, such as a page fault or a memory access violation. Hence the response to an ABORT interrupt is different in behavior than that of IRQ and/or NMI when asserted. Also, achieving correct operation in response to ABORT requires that the interrupt occur at the proper time during the machine cycle, whereas no such requirement exists for IRQ or NMI.

When ABORT is asserted during a valid memory cycle (that is, when the processor has asserted the VDA and/or VPA status outputs), the following sequence of events will occur:

1. The processor completes the current instruction but does not change the registers or memory in any way—the results of the completed instruction are discarded.
2. The program bank (PB, see above) is pushed to the stack.
3. The most significant byte (MSB) of the aborted instruction's address is pushed onto the stack.
4. The least significant byte (LSB) of the aborted instruction's address is pushed onto the stack.
5. The status register is pushed onto the stack.
6. The interrupt disable flag is set in the status register.
7. PB is loaded with $00.
8. The program counter is loaded from the ABORT vector (see tables).

As the address pushed to the stack is that of the aborted instruction rather than the contents of the program counter, executing an RTI (ReTurn from Interrupt) following an ABORT interrupt will cause the processor to return to the aborted instruction, rather than the next instruction, as would be the case with the other interrupts.

In order for the processor to correctly respond to ABORT, system logic must assert the interrupt as soon as a valid address has been placed on the bus and it has been determined that the address constitutes a page fault or a memory access violation. Hence the logic must not assert ABORT until the processor has asserted the VDA or VPA signals. Also, ABORT must remain asserted until the fall of the phase-two clock and then be immediately released. If these timing constraints are not observed, the ABORT interrupt handler itself may be aborted, causing registers and/or memory to be changed in a possibly-undefined manner.