Instruction Pipeline - Illustrated Example

Illustrated Example

To the right is a generic pipeline with four stages:

  1. Fetch
  2. Decode
  3. Execute
  4. Write-back

The top gray box is the list of instructions waiting to be executed; the bottom gray box is the list of instructions that have been completed; and the middle white box is the pipeline.

Execution is as follows:

Time Execution
0 Four instructions are waiting to be executed
1
  • the green instruction is fetched from memory
2
  • the green instruction is decoded
  • the purple instruction is fetched from memory
3
  • the green instruction is executed (actual operation is performed)
  • the purple instruction is decoded
  • the blue instruction is fetched
4
  • the green instruction's results are written back to the register file or memory
  • the purple instruction is executed
  • the blue instruction is decoded
  • the red instruction is fetched
5
  • the green instruction is completed
  • the purple instruction is written back
  • the blue instruction is executed
  • the red instruction is decoded
6
  • The purple instruction is completed
  • the blue instruction is written back
  • the red instruction is executed
7
  • the blue instruction is completed
  • the red instruction is written back
8
  • the red instruction is completed
9 All four instructions are executed

Read more about this topic:  Instruction Pipeline

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