XBurst Embedded CPUs
The XBurst CPU architecture is compatible with MIPSII and has a 8-staged pipeline. XBurst CPU technology consists of 2 parts:
- A RISC/SIMD/DSP hybrid instruction set architecture which enables the processor to have the capability of computation, signal processing and video processing.
- An innovative pipeline engine which consumes very little power while emitting instructions. The processor core (including L1 cache) consumes 100 mW at 1000 MHz at a 65 nm LP process.
Read more about this topic: Ingenic Semiconductor
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