The RS64-III or Pulsar was introduced in 1999 at 450 MHz. Key changes included larger 128 KiB L1 instruction and data caches, improved branch prediction accuracy and reduced branch misprediction penalties of zero or one cycle. The RS64-III has a five stage pipeline and a 256 bit wide L2 cache bus, which provided the processor with 14.4 GB/s of bandwidth from the 8 MiB L2 cache, implemented with 225 MHz DDR SRAMs.
The RS64-III has 34 million transistors, a die size of 140 mm², and is manufactured on the 0.22 μm CMOS 7S process with six levels of copper interconnect.
In 2000, IBM launched a refined version called IStar manufactured with a SOI fabrication process with copper interconnects, which increased the processor's clock frequency to 600 MHz. This was the first processor implemented in this process. Architecturally however, the IStar was identical to Pulsar.
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