The RS64-II or Northstar was introduced at 262 MHz in 1998 with 8 MB of full speed L2 on a 256 bit 6XX bus (also used in PowerPC 620 and POWER3). Processor boards containing 4 RS64-II's could be swapped into machines designed for similar 4-way RS64 boards, avoiding a "fork lift upgrade". The RS64-II contained 12.5 million transistors, was 162 mm² large and drew 27 Watts maximum power. Manufacturing changed to a 0.35 μm CMOS fabrication.
RS64-II was the first mass-market processor to implement multithreading. Essentially, each chip stores state information for 2 threads at any given time and appears to be two processors to the OS. One logical processor runs what is called the foreground thread. When this thread encounters a high latency event (L2 cache miss, etc.) the background thread is switched to, on the second logical processor from the OS's point of view. In the event of a "less long" latency event (L1 miss, etc.), thread switching will only occur if the background thread is ready to execute. If the background thread is also waiting for a miss, thread switching will not occur. IBM calls this scheme "coarse grained multithreading". It is not exactly the same thing as simultaneous multithreading as found on later Pentium 4 processors. An IBM paper notes that the coarse grained scheme is a better fit for an in-order architecture like RS64.
RS64-II was called A50 in AS/400 systems.
Read more about this topic: IBM RS64