Description
The CP1600's instruction set closely followed the PDP-11's, but was not entirely compatible. The instruction opcode was only 10 bits, with the remaining 6 marked "Reserved for future expansion". It appears that the extra 6 bits were intended to be used with co-processors, asserting the PCIT line which stalled the CPU until released. Instructions might be one to three words long depending on the addressing format being used. Unlike similar CPUs, the CP1600 did not support memory-memory indirect addressing (offsets), and looping was implemented in a different way which allowed it to run much faster.
Like the PDP-11, the CP1600 used eight 16-bit "general purpose" processor registers, although they were not truly general purpose as in modern designs. Only R0 was truly general purpose and has been described as "the primary accumulator". R1 through R3 were data counters, generally used for register-based addressing ("implied addressing"). R4 and R5 auto-incremented after being accessed, which made them useful for looping over collections of data.
R6 was the stack pointer, R7 the program counter. Since both of these registers were visible to the programmer, they could be used to implement multiple stacks, or support more complex branching, among other things. There were no implicit stack instructions; when R6 was used in a "read" operation it decremented the address and then returned the data being pointed at, simulating a POP, and when it was used in a "write" it would post-increment (like R4/R5) and write, like a PUSH.
Like the PDP-11, one of the CP1600's notable features was the use of memory-mapped I/O, meaning that devices were controlled by writing to certain locations in memory. Unlike the PDP-11's Unibus, however, the CP1600 multiplexed its data and address lines in order to reduce pin count and fit into a 40-pin DIP. This change meant that implementations had to use latches or buffers to be able to interface with the CPU as it changed the bus from indicating an address to data. This negatively affected I/O performance, and to address this problem GI designed the "Programmable Interface Controller" which was designed to work in concert with the CP1600 as a channel controller.
The CP1600 was implemented in nMOS and required +12, +5, -3 V power supplies; most internal logic was implemented in TTL (5 V). It had a 3.3 MHz clock (300 ns cycle time) that was later bumped to 5 MHz clock (200 ns cycle time), instructions executed within 1.6 and 4.8 microseconds. GI also produced a development system for the CP1600, the "GIMINI".
Read more about this topic: General Instrument CP1600
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