XGATE
The XGATE co-processor is a 16-bit RISC processor operating at twice the main bus clock. It offloads work from the S12X core by handling interrupts only and does not run a background loop. The first versions of the XGATE do not allow for higher priority interrupts to pre-empt a currently handled interrupt, but the "XGATEV3" as featured in the 9S12XEP100 (and others) does allow this. The S12X can trigger software interrupts on the XGATE core and vice-versa. A semaphore system is implemented to allow the S12X and XGATE cores to synchronize access to peripherals.
Typically the XGATE code is copied to RAM at device startup and then executed from RAM for a speed benefit. The XGATE has a partial 64KByte address space with no paging. The registers share addresses, but the flash and ram appear at different addresses between the cores. (See the datasheet for more details.)
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