Freescale 68HC12 - MC9S12X Derivatives

MC9S12X Derivatives

The MC9S12XDP512 which was introduced in 2004 has a bus speed of 40 MHz and a peripheral co-processor known as the XGATE which allows for some tasks to be offloaded from the CPU. The CPU of the S12X derivative also features several new instructions to increase performance.

Freescale announced the MC9S12XEP100 in May 2006 to further extend the S12X family to 50MHz bus speed and add a Memory protection unit (based on segmentation) and a hardware scheme to provide Emulated EEPROM. HCS12 products contain a single processor, the HCS12X feature the additional XGATE peripheral processor.

The S12X family offer two main methods to address more than 64KBytes.

• Paged memory regions in the 64KByte local map: PPAGE for paged program data, RPAGE for paged RAM, EPAGE for paged EEPROM/flash
• Global addressing permits access to any addresses in the 8 MByte address space. GPAGE is used in conjunction with special opcodes. (gldaa etc.)