Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
Read more about Formal Equivalence Checking: Equivalence Checking and Levels of Abstraction, Synchronous Machine Equivalence, Methods, Commercial Applications For Equivalence Checking, Generalizations
Famous quotes containing the word formal:
“True variety is in that plenitude of real and unexpected elements, in the branch charged with blue flowers thrusting itself, against all expectations, from the springtime hedge which seems already too full, while the purely formal imitation of variety ... is but void and uniformity, that is, that which is most opposed to variety....”
—Marcel Proust (1871–1922)