Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
Read more about Formal Equivalence Checking: Equivalence Checking and Levels of Abstraction, Synchronous Machine Equivalence, Methods, Commercial Applications For Equivalence Checking, Generalizations
Famous quotes containing the word formal:
“Two clergymen disputing whether ordination would be valid without the imposition of both hands, the more formal one said, “Do you think the Holy Dove could fly down with only one wing?””
—Horace Walpole (1717–1797)