Taxonomy of Yield Loss Mechanisms
The most important yield loss models (YLMs) for VLSI ICs can be classified into several categories based on their nature.
- Functional yield loss is still the dominant factor and is caused by mechanisms such as misprocessing (e.g., equipment-related problems), systematic effects such as printability or planarization problems, and purely random defects.
- High-performance products may exhibit parametric design marginalities caused by either process fluctuations or environmental factors (such as supply voltage or temperature).
- The test-related yield losses, which are caused by incorrect testing, can also play a significant role.
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