Design For Manufacturability
After understanding the causes of yield loss, the next step is to make the design as resistant as possible. Techniques used for this include:
- Substituting higher yield cells where permitted by timing, power, and routability.
- Changing the spacing and width of the interconnect wires, where possible
- Optimizing the amount of redundancy in internal memories.
- Substituting fault tolerant (redundant) vias in a design where possible
All of these require a detailed understanding of yield loss mechanisms, since these changes trade off against one another. For example, introducing redundant vias will reduce the chance of via problems, but increase the chance of unwanted shorts. Whether this is good idea, therefore, depends on the details of the yield loss models and the characteristics of the particular design.
Read more about this topic: Design For Manufacturability (IC)
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