Statistical Delay Calculation
See also: Statistical static timing analysisAs chip dimensions get smaller, the delays of both gates and wires may need to be treated as statistical estimates instead of deterministic quantities. For gates, this requires extensions to the library formats. For wires, this requires methods that can calculate the means and distributions of wire delays. In both cases it is critical to capture the dependence on the underlying variables such a threshold voltage and metal thickness, since these result in correlations among the delays of nearby components. See for an early example.
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