Classic RISC Pipeline
In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000, and later DLX.
Each of these classic scalar RISC designs fetched and attempted to execute one instruction per cycle. The main common concept of each design was a five-stage execution instruction pipeline. During operation, each pipeline stage would work on one instruction at a time.
Each of these stages consisted of an initial set of flip-flops, and combinational logic which operated on the outputs of those flops.
Read more about Classic RISC Pipeline: Hazards, Exceptions, Cache Miss Handling
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