Burroughs Large Systems - History

History

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The first of the Burroughs large systems was the B5000. Designed in 1961, it was a second-generation computer using discrete transistor logic and magnetic core memory. The successor machines followed the hardware development trends to re-implement the architecture in new logic over the next 25 years, with the B5500, B6500, B5700, B6700, B7700, B6800, B7800, and finally the Burroughs A series. After a merger in which Burroughs acquired Sperry Corporation and changed its name to Unisys, the company continued to develop new machines based on the MCP CMOS ASIC. These machines were the Libra 100 through the Libra 500, With the Libra 590 being announced in 2005. Later Libras, including the 590, also incorporate Intel Xeon processors and can run the Burroughs large systems architecture in emulation as well as on the MCP CMOS processors. It is unclear if Unisys will continue development of new MCP CMOS ASICs.

Burroughs (1961–1986)
B5000 1961 initial system, 2nd generation (transistor) computer
B5500 1964 3x speed improvement(?)
B6500 1969 3rd gen computer (integrated circuits), up to 4 processors
B5700 1971 new name for B5500
B6700 1971 new name/bug fix for B6500
B7700 1972 faster processor, cache for stack, up to 8 requestors (IO or Central processors) in one or two partitions.
B6800 1977? semiconductor memory, NUMA architecture
B7800 1977? semiconductor memory, faster, up to 8 requestors (IO or Central processors) in one or two partitions.
B5900 1980? semiconductor memory, NUMA architecture. Max of 4 B5900 CPUs bound to a local memory and a common Global Memory II (tm)
B6900 1979? semiconductor memory, NUMA architecture. Max of 4 B6900 CPUs bound to a local memory and a common Global Memory(tm)
B7900 1982? semiconductor memory, faster, code & data caches, NUMA architecture,

1-2 HDUs (IO), 1-2 APs, 1-4 CPUs, Soft implementation of NUMA memory allowed CPUs to float from memory space to memory space.

A9/A10 1984 B6000 class, First piplined processor in the mid-range, single CPU (dual on A10), First to support eMode Beta (expanded Memory Addressing)
A12/A15 1985 B7000 class, Re-implemented in custom-designed Motorola ECL MCA1, then MCA2 gate arrays, single CPU single HDU (A12) 1-4 CPU, 1-2 HDU (A15)
Unisys (1986–present))
Micro A 1989 desktop "mainframe" with single-chip SCAMP processor.
Clearpath HMP NX 4000 198? ??
Clearpath HMP NX 5000 199? ??
Clearpath HMP LX 5000 1998 Implements Burroughs Large systems in emulation only (Xeon processors)
Libra 100 2002? ??
Libra 200 200? ??
Libra 300 200? ??
Libra 400 200? ??
Libra 500 2005? e.g. Libra 595
Libra 600 2006? ??

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