Berkeley RISC - Follow-ons

Follow-ons

Work on the original RISC designs ended with RISC II, but the concept itself lived on at Berkeley. The basic core was re-used in SOAR in 1984, basically a RISC converted to run Smalltalk (in the same way that it could be claimed RISC ran C), and later in the similar VLSI-BAM that ran PROLOG instead of Smalltalk. Another effort was SPUR, which was a full set of chips needed to build a complete 32-bit workstation.

RISC is less famous, but more influential, for being the basis of the commercial SPARC processor design from Sun Microsystems. It was the SPARC that first clearly demonstrated the power of the RISC concept; when they shipped in the first SPARCstations they outperformed anything on the market. This led to virtually every Unix vendor hurrying for a RISC design of their own, leading to designs like the DEC Alpha and PA-RISC, while SGI purchased MIPS Computer Systems. By 1986 most large chip vendors followed, working on efforts like the Motorola 88000, Fairchild Clipper, AMD 29000 and the PowerPC.

Techniques developed for and alongside the idea of the reduced instruction set have also been adopted in successively more powerful implementations and extensions of the traditional "complex" x86 architecture. Much of a modern microprocessor's transistor count is devoted to large caches, many pipeline stages, superscalar instruction dispatch, branch prediction and other modern techniques which are applicable regardless of instruction architecture. The amount of silicon dedicated to instruction decoding on a modern x86 implementation is proportionately quite small, so the distinction between "complex" and RISC processor implementations has become blurred.