Implementations
The AVR32 architecture is solely used in Atmel's own products. Atmel launched in 2006 the first implementation of the AVR32 architecture: the AVR32 AP7 core, a 7-stage pipelined, cache-based design platform. This "AP7000" implementation of the AVR32B architecture supports SIMD (single instruction multiple data) DSP (digital signal processing) instructions to the RISC instruction-set, in addition to Java hardware acceleration. It includes a Memory Management Unit (MMU) and supports operating systems like Linux. In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips.
In 2007, Atmel launched the second implementation of the AVR32 architecture: the AVR32 UC3 core. This is designed for microcontroller usage, using on-chip flash memory for program storage and running without an MMU. The AVR32 UC3 core uses a three-stage pipelined Harvard architecture specially designed to optimize instruction fetches from on-chip flash memory. The AVR32 UC3 core implements the AVR32A architecture. It shares the same instruction set architecture (ISA) as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support. Still, it shares over 220 instructions. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point DSP arithmetic.
Both implementations build on a set of peripheral controllers and bus designs first seen in the AT91SAM ARM-based platforms. Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products.
Both AVR32 implementations include a Nexus class 2+ based On-Chip Debug framework build with JTAG.
The UC3 C, announced at the Electronica 2010 in Munich Germany on November 10, 2010, is the first 32-bit AVR microcontroller with a floating-point unit.
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