Architecture
The AVR32 Architecture consists of several micro-architectures, most notably the AVR32A and AVR32B architectures, which describe fixed additions to the Instruction Set Architecture, configurations of the register file and the use of instruction and data-caches. The AVR32A microarchitecture is targeted at cost-sensitive applications, and so does not provide dedicated hardware registers for shadowing of register file registers, status and return address in interrupt contexts. This saves chip area at the expense of slower interrupt handling. The AVR32B, on the other hand, is targeted at applications where interrupt latency is important, so it implements dedicated registers to hold these values for interrupts, exceptions and supervisor calls.
The AVR32 architecture supports a Java Virtual Machine hardware implementation.
The AVR32 Instruction Set Architecture consists of 16-bit (compact) and 32-bit (extended) instructions, with several specialized instructions not found in architectures like MIPS32 or ARMv5 or ARMv6 ISA. Several U.S. patents are filed for the AVR32 ISA and design platform.
Just like the AVR 8-bit microcontroller architecture, the AVR32 was designed for extremely efficient code density and performance per clock cycle. Atmel used the independent benchmark consortium EEMBC to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (THUMB) code and ARMv5 32-bit (ARM) code by as much as 50% on code-size and 3X on performance.
Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48 mW/MHz in active mode, which it claims is less power than any other 32-bit CPU.
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