New Features
The width of the SIMD register file is increased from 128 bits to 256 bits, and renamed from XMM0–XMM15 to YMM0–YMM15. In processors with AVX support, the legacy SSE instructions (which previously operated on 128-bit XMM registers) now operate on the lower 128 bits of the YMM registers.
AVX introduces a three-operand SIMD instruction format, where the destination register is distinct from the two source operands. For example, an SSE instruction using the conventional two-operand form a = a + b can now use a non-destructive three-operand form c = a + b, preserving both source operands. AVX's three-operand format is limited to the instructions with SIMD operands (YMM), and does not include instructions with general purpose registers (e.g. EAX). Such support will first appear in AVX2.
The alignment requirement of SIMD memory operands is relaxed.
Read more about this topic: Advanced Vector Extensions
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