Technology Demos
On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm2. The cell was printed using immersion lithography.
The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology mode designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm2, smallest reported to date.
On January 3, 2010, Intel and Micron Technology Inc. announced the first in a family of 25 nm NAND devices.
On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a technology called 3-D Tri-Gate.
On October 19, 2011, Intel CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun.
Processors using the POWER8 instruction set will also be produced in a 22 nm SOI process.
Read more about this topic: 22 Nanometer
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