Verilog - Initial and Always

Initial and Always

There are two separate ways of declaring a Verilog process. These are the always and the initial keywords. The always keyword indicates a free-running process. The initial keyword indicates a process executes exactly once. Both constructs begin execution at simulator time 0, and both execute until the end of the block. Once an always block has reached its end, it is rescheduled (again). It is a common misconception to believe that an initial block will execute before an always block. In fact, it is better to think of the initial-block as a special-case of the always-block, one which terminates after it completes for the first time.

//Examples: initial begin a = 1; // Assign a value to reg a at time 0 #1; // Wait 1 time unit b = a; // Assign the value of reg a to reg b end always @(a or b) // Any time a or b CHANGE, run the process begin if (a) c = b; else d = ~b; end // Done with this block, now return to the top (i.e. the @ event-control) always @(posedge a)// Run whenever reg a has a low to high change a <= b;

These are the classic uses for these two keywords, but there are two significant additional uses. The most common of these is an always keyword without the @(...) sensitivity list. It is possible to use always as shown below:

always begin // Always begins executing at time 0 and NEVER stops clk = 0; // Set clk to 0 #1; // Wait for 1 time unit clk = 1; // Set clk to 1 #1; // Wait 1 time unit end // Keeps executing - so continue back at the top of the begin

The always keyword acts similar to the "C" construct while(1) {..} in the sense that it will execute forever.

The other interesting exception is the use of the initial keyword with the addition of the forever keyword.

The example below is functionally identical to the always example above.

initial forever // Start at time 0 and repeat the begin/end forever begin clk = 0; // Set clk to 0 #1; // Wait for 1 time unit clk = 1; // Set clk to 1 #1; // Wait 1 time unit end