Technology and Key Features
Verilator converts synthesizable Verilog to C++ or SystemC. It can handle all versions of Verilog and also some SystemVerilog and Sugar/PSL assertions. The approach is closer to synthesis than event driven simulation. The entire design is flattened (that is all modules are expanded, to create one module). Static analysis is used to eliminate wires and schedule all processes at model generation time. Since this is a cycle accurate model, all intra-cycle delays are ignored. A C++ class is generated with a function which will take 2-state values on input ports and advance them to values on output ports at the next clock edge.
SystemC is supported by providing a wrapper class using SystemC ports, and with sensitivity to the clock(s), which will drive the ports of the underlying C++ model.
Read more about this topic: Verilator
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