Time Stamp Counter - Implementation in Various Processors

Implementation in Various Processors

Intel processor families increment the time-stamp counter differently:

• For Pentium M processors (family, models ); for Pentium 4 processors, Intel Xeon processors (family, models ); and for P6 family processors: the time-stamp counter increments with every internal processor clock cycle. The internal processor clock cycle is determined by the current core-clock to busclock ratio. Intel SpeedStep technology transitions may also impact the processor clock.

• For Pentium 4 processors, Intel Xeon processors (family, models ); for Intel Core Solo and Intel Core Duo processors (family, model ); for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family, model ); for Intel Core 2 and Intel Xeon processors (family, display_model ); for Intel Atom processors (family, display_model ): the time-stamp counter increments at a constant rate. That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may differ from the maximum qualified frequency of the processor.

The specific processor configuration determines the behavior. Constant TSC behavior ensures that the duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if the processor core changes frequency. This is the architectural behavior moving forward for all Intel processors.

AMD processors up to the K8 core always incremented the time-stamp counter every clock cycle. Thus, power management features were able to change the number of increments per second, and the values could get out of sync between different cores or processors in the same system. For Windows, AMD provides a utility to periodically synchronize the counters on multiple core CPUs. Since the family 10h (Barcelona/Phenom), AMD chips feature a constant TSC, which can be driven either by the HyperTransport speed or the highest P state. A CPUID bit (Fn8000_0007:EDX_8) advertises this.