Technical Details
The interface consists of (per direction):
- sixteen LVDS pairs for the data path
- one LVDS pair for control
- one LVDS pair for clock at half of the data rate
- two FIFO status lines running at 1/8 of the data rate
- one status clock
The clocking is Source-synchronous and operates around 700 MHz. Implementations of SPI-4.2 (PL-4) have been produced which allow somewhat higher clock rates. This is important when overhead bytes are added to incoming packets.
Read more about this topic: PL-4
Famous quotes containing the words technical and/or details:
“The best work of artists in any age is the work of innocence liberated by technical knowledge. The laboratory experiments that led to the theory of pure color equipped the impressionists to paint nature as if it had only just been created.”
—Nancy Hale (b. 1908)
“Patience is a most necessary qualification for business; many a man would rather you heard his story than granted his request. One must seem to hear the unreasonable demands of the petulant, unmoved, and the tedious details of the dull, untired. That is the least price that a man must pay for a high station.”
—Philip Dormer Stanhope, 4th Earl Chesterfield (1694–1773)