Technical Details
The interface consists of (per direction):
- sixteen LVDS pairs for the data path
- one LVDS pair for control
- one LVDS pair for clock at half of the data rate
- two FIFO status lines running at 1/8 of the data rate
- one status clock
The clocking is Source-synchronous and operates around 700 MHz. Implementations of SPI-4.2 (PL-4) have been produced which allow somewhat higher clock rates. This is important when overhead bytes are added to incoming packets.
Read more about this topic: PL-4
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