Logical Effort - Derivation of Delay in A Logic Gate

Derivation of Delay in A Logic Gate

Delay is expressed in terms of a basic delay unit, τ = 3RC, the delay of an inverter driving an identical inverter with no parasitic capacitance; the unitless number associated with this is known as the normalized delay. (Some authors prefer define the basic delay unit as the fanout of 4 delay—the delay of one inverter driving 4 identical inverters). The absolute delay is then simply defined as the product of the normalized delay of the gate, d, and τ:

In a typical 600-nm process τ is about 50 ps. For a 250-nm process, τ is about 20 ps. In modern 45 nm processes the delay is approximately 4 to 5 ps.

The normalized delay in a logic gate can be expressed as a summation of two primary factors: parasitic delay, p (which is an intrinsic delay of the gate and can be found by considering the gate driving no load), and stage effort, f (which is dependent on the load as described below). Consequently,

The stage effort is divided into two components: a logical effort, g, which is the ratio of the input capacitance of a given gate to that of an inverter capable of delivering the same output current (and hence is a constant for a particular class of gate and can be described as capturing the intrinsic properties of the gate), and an electrical effort, h, which is the ratio of the input capacitance of the load to that of the gate. Note that "logical effort" does not take the load into account and hence we have the term "electrical effort" which takes the load into account.The stage effort is then simply:

Combining these equations yields a basic equation that models the normalised delay through a single logic gate: