Logic Simulation - Length of Simulation

Length of Simulation

The level of effort required to debug and then verify the design is proportional to the maturity of the design. That is, early in the design’s life, bugs and incorrect behavior are usually found quickly. As the design matures, the simulation will require more time and resources to run, and errors will take progressively longer to be found. This is particularly problematic when simulating components for modern-day systems; every component that changes state in a single clock cycle on the simulation will require several clock cycles to simulate.

A straightforward approach to this issue may be to emulate the circuit on a field-programmable gate array instead. Formal verification can also be explored as an alternative to simulation, although a formal proof is not always possible.

A prospective way to accelerate logic simulation is using distributed and parallel computations.

To help gauge the thoroughness of a simulation, tools exist for assessing code coverage, functional coverage and logic coverage tools.

Read more about this topic:  Logic Simulation

Famous quotes containing the words length of, length and/or simulation:

    Twenty-four-hour room service generally refers to the length of time that it takes for the club sandwich to arrive. This is indeed disheartening, particularly when you’ve ordered scrambled eggs.
    Fran Lebowitz (b. 1950)

    The grace of novelty and the length of habit, though so very opposite to one another, yet agree in this, that they both alike keep us from discovering the faults of our friends.
    François, Duc De La Rochefoucauld (1613–1680)

    Life, as the most ancient of all metaphors insists, is a journey; and the travel book, in its deceptive simulation of the journey’s fits and starts, rehearses life’s own fragmentation. More even than the novel, it embraces the contingency of things.
    Jonathan Raban (b. 1942)