Front-side Bus - Evolution

Evolution

The front-side bus had the advantage of high flexibility and low cost. Simple symmetric multiprocessors place a number of CPUs on an FSB, though performance does not scale linearly due to the architecture's bandwidth bottleneck.

The front-side bus was used in all of Intel's Atom, Celeron, Pentium, Core 2, and Xeon processor models through about 2008. Originally, this bus was a central connecting point for all system devices and the CPU. The speed of a faster CPU is wasted if it cannot fetch instructions and data as fast as it can execute them. The CPU must wait for one or more clock cycles until the memory returns its value, or access other devices attached to the FSB if it becomes a bottleneck.

The front-side bus was criticized by AMD as being an old and slow technology that limits system performance. More modern designs use point-to-point connections like AMD's HyperTransport and Intel's QuickPath Interconnect (QPI). FSB's fastest transfer speed was 1.6 GT/s, which provided only 80% of the theoretical bandwidth of a 16-bit HyperTransport 3.0 link as implemented on AM3 Phenom II CPUs, only half of the bandwidth of a 6.4 GT/s QuickPath Interconnect link, and only 25% of the bandwidth of a 32-bit HyperTransport 3.1 link. In addition, in an FSB-based architecture, the memory must be accessed via the FSB. In HT- and QPI-based systems, the memory is accessed independently by means of a memory controller on the CPU itself, freeing bandwidth on the HyperTransport or QPI link for other uses.