EUVL Demonstrations
Interference lithography at the Paul Scherrer Institute has been used to demonstrate sub-10 nm line-space features at . The resist performance tested with this source does not reflect the performance expected for an EUV projection tool due to the limited contrast of projection tools.
In 1996, a collaboration between Sandia National Laboratories, University of California at Berkeley, and Lucent Technologies, produced NMOS transistors with gate lengths from 75 nm to 180 nm. The gate lengths were defined by EUV lithography. The device saturation current at 130 nm gate length was ~0.2 mA/um. A 100 nm gate device showed subthreshold swing of 90 mV/decade and saturated transconductance of 250 mS/mm. A commercial NMOS at the same design rule patterned by then-state-of-the-art DUV lithography showed 0.94 mA/um saturation current and 860 mS/mm saturated transconductance. The subthreshold swing in this case was less than 90 mV/decade.
In February 2008, a collaboration including IBM and AMD, based at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York, used EUV lithography to pattern 90 nm trenches in the first metal layer of a 45 nm node test chip. No specific details on device performance were given. However, the lithographic performance details given still indicated much to be desired:
- CD uniformity: 6.6%
- Overlay: 17.9 nm x, 15.6 nm y, possibly correctable to 6.7 nm x, 5.9 nm y
- Power: 1 W at wafer (>200 W required for high volume), with a dose of 3.75 mJ/cm2
- Defects: 1/sq. cm.
The high defect level may not be unexpected as AMD's 45 nm node Metal 1 design rule was 90 nm while the same EUV exposure theoretically could result in printed defects below 30 nm originating from mask defects larger than 100 nm. Optical lithography pushed beyond its natural resolution limit has a significant advantage in this regard.
Apparently, the CNSE EUV tool suffered from a well-known 16% flare problem. Flare effects may be difficult to separate from the secondary electron effects discussed earlier.
Also in July 2008, IMEC printed ~60 nm contacts using their installed EUV tool. Doses of 12–18 mJ/cm2 were used.
In August 2008, SEMATECH demonstrated a 22 nm half-pitch using chemically-amplified photoresist. However, even at 15 mJ/cm2, the linewidth roughness was very significant, 5–6 nm, so that even the image pitch regularity was challenged.
In April 2009, IMEC fabricated 22 nm SRAM cells where the contact and Metal 1 layers (~45 nm design rule) were printed with EUV lithography. However, it was acknowledged that EUV would not be ready when companies start using 22 nm. In addition, it was commented that the feature edge profiles indicated slope asymmetry related to the characteristic EUV illumination asymmetry. Whereas this demonstration only focused on a limited number of ~45 nm features, Intel's shot noise calculation above for billions of features ~30 nm indicates difficult challenges ahead for manufacturing.
In late 2009, KLA-Tencor and GlobalFoundries along with Lawrence Berkeley National Labs published a paper which showed the stochastic behavior of EUV-generated secondary electrons in EUV resists. In particular, 32 nm half-pitch trenches showed significant edge roughness, width roughness and critical dimension (CD) variability. It may also explain the ~ 15 nm resist blur observed in an earlier study.
Read more about this topic: Extreme Ultraviolet Lithography