Dynamic Logic (digital Electronics) - Static Versus Dynamic Logic

Static Versus Dynamic Logic

The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.

In most types of logic design, termed static logic, there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply voltage or the ground. As a sidenote, there is of course an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.

In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, its impedance causes it to maintain a level within some tolerance range of the driven level.

Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.

Static logic has no minimum clock rate—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to two advantages:

• being able to pause a system at any time makes debugging and testing much easier, enabling techniques such as single stepping.
• being able to run a system at extremely low clock rates allows low-power electronics to run longer on a given battery.

Being able to pause a system at any time for any duration can also be used to synchronize to asynchronous events. (While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins, or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. )

In particular, although many popular CPUs use dynamic logic, only static cores—CPUs designed with fully static CMOS technology—are usable in space satellites due to their higher radiation hardness

Dynamic logic, when properly designed, can be over twice as fast as static logic. It uses only the faster N transistors, which improve transistor sizing optimizations. Static logic is slower because it has twice the capacitive loading, higher thresholds, and uses slow P transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days require the use of dynamic, although some manufacturers such as Intel have completely switched to static logic to reduce power consumption. Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost.

In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS. There are several powersaving techniques that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.