Dynamic Logic (digital Electronics) - Dynamic Logic Example

Dynamic Logic Example

As an example, consider first the static logic implementation of a NAND gate (here in CMOS):

This circuit implements the logic function

If A and B are both high, the output will be pulled low, whereas if one of A and B are low, the output will be pulled high. Most importantly, though, at all times, the output is pulled either low or high.

Consider now a dynamic logic implementation:

The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.

During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).

Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must be sample it synchronously during the time that it is valid.

Also, when both A and B are high, so that the output is low, the circuit will pump one capacitor-load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the A and B inputs are constant and both high, the dynamic NAND gate uses power in proportion to the clock rate, as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low, but this in turn reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation just mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit which derives from an equilibrium between clock speed and load capacitance.

A popular implementation is domino logic.