Instruction Encoding
Bit assignments:
- rrrrr = Source register
- rrrr = Source register pair
- ddddd = Destination register
- dddd = destination register pair
- hhhh = High register, R16–R31
- pp = Register pair, W, X, Y or Z
- y = Y/Z register pair bit (0=Z, 1=Y)
- s = Store/load bit (0=load, 1=store)
- c = call/jump (0=jump, 1=call)
- aaaaaa = I/O space address
- aaaaa = I/O space address (first 32 only)
- bbb = Bit number
- B = Bit value
- kkkkkk = 6-bit unsigned constant
- KKKKKKKK = 8-bit constant
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/store with offset instructions are the most extreme example. where a 6-bit offset is broken into 3 pieces.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | d d d d | r r r r | MOVW Move register pair | ||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | d d d | r r r | Signed and fractional multiply (R16–R23 only) | |||||||
| 0 | 0 | 0 | 0 | 0 | 1 | r | d d d d d | r r r r | 2-operand instructions CPC, SBC, ADD, CPSE, CP, SUB. ADC, AND, EOR, OR, MOV |
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| 0 | 0 | 0 | 0 | 1 | ||||||||||||
| 0 | 0 | 0 | 1 | |||||||||||||
| 0 | 0 | 1 | 0 | |||||||||||||
| 0 | 0 | 1 | 1 | K K K K | h h h h | K K K K | Register-immediate instructions CPI, SBCI, SUBI, ORI, ANDI |
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| 0 | 1 | |||||||||||||||
| 1 | 0 | k | 0 | k k | s | d d d d d | y | k k k | LDD/STD to Z+k or Y+k | |||||||
| 1 | 0 | 0 | 1 | 0 | 0 | s | d d d d d | LD/ST other | ||||||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 0 | 1-operand instructions (COM, NEG, SWAP, etc.) | |||||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | B̅ | b b b | 1 | 0 | 0 | 0 | SEx/CLx Status register clear/set bit | ||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | Misc instructions (RET, RETI, SLEEP, etc.) | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | c | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Indirect jump/call to Z or EIND:Z | |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | d d d d d | 1 | 0 | 1 | 0 | DEC Rd | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | k k k k | 1 | 0 | 1 | 1 | DES round k | |||
| 1 | 0 | 0 | 1 | 0 | 1 | 0 | k k k k k | 1 | 1 | c | k | JMP/CALL abs22 | ||||
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | k k | p p | k k k k | ADIW/SBIW Rp,uimm6 | ||||||
| 1 | 0 | 0 | 1 | 1 | 0 | B | a a a a a | b b b | I/O space bit operations | |||||||
| 1 | 0 | 0 | 1 | 1 | 1 | r | d d d d d | r r r r | MUL, unsigned: R1:R0 = Rr×Rd | |||||||
| 1 | 0 | k | 0 | k k | s | d d d d d | y | k k k | See 10k0 above |
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| 1 | 0 | 1 | 1 | s | a a | d d d d d | a a a a | OUT/IN to I/O space | ||||||||
| 1 | 1 | 0 | c | 12 bit signed offset | Relative jump/call to PC ± 2×simm12 | |||||||||||
| 1 | 1 | 1 | 0 | K K K K | h h h h | K K K K | LDI Rh,K | |||||||||
| 1 | 1 | 1 | 1 | 0 | B̅ | 7-bit signed offset | b b b | Conditional branch on status register bit | ||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | s | d d d d d | 0 | b b b | BLD/BST register bit to STATUS.T | ||||||
| 1 | 1 | 1 | 1 | 1 | 1 | B | d d d d d | 0 | b b b | SBRC/SBRS skip if register bit equals B | ||||||
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