X86 Architecture - Addressing Modes

Addressing Modes

Addressing modes for 16-bit x86 processors can be summarized by this formula:

$\begin{Bmatrix}CS:\\DS:\\SS:\\ES:\end{Bmatrix} \begin{bmatrix}\begin{Bmatrix}BX\\BP\end{Bmatrix}\end{bmatrix} + \begin{bmatrix}\begin{Bmatrix}SI\\DI\end{Bmatrix}\end{bmatrix} + \rm$

Addressing modes for 32-bit address size on 32-bit or 64-bit x86 processors can be summarized by this formula:

$\begin{Bmatrix}CS:\\DS:\\SS:\\ES:\\FS:\\GS:\end{Bmatrix} \begin{bmatrix}\begin{Bmatrix}EAX\\EBX\\ECX\\EDX\\ESP\\EBP\\ESI\\EDI\end{Bmatrix}\end{bmatrix} + \begin{bmatrix}\begin{Bmatrix}EAX\\EBX\\ECX\\EDX\\EBP\\ESI\\EDI\end{Bmatrix}*\begin{Bmatrix}1\\2\\4\\8\end{Bmatrix}\end{bmatrix} + \rm$

Addressing modes for 64-bit code on 64-bit x86 processors can be summarized by this formula:

$\begin{Bmatrix} \begin{Bmatrix}FS:\\GS:\end{Bmatrix} \begin{bmatrix}{\rm general\;register}\end{bmatrix} + \begin{bmatrix}{\rm general\;register}*\begin{Bmatrix}1\\2\\4\\8\end{Bmatrix}\end{bmatrix}\\\\ RIP \end{Bmatrix} + \rm$

Instruction relative addessing in 64-bit code (RIP + displacement, where RIP is the instruction pointer register) simplifies the implementation of position-independent code (as used in shared libraries in some operating systems).

The 8086 had 64 kB of 8-bit (or alternatively 32 K-word of 16-bit) I/O space, and a 64 kB (one segment) stack in memory supported by computer hardware. Only words (2 bytes) can be pushed to the stack. The stack grows downwards (toward numerically lower addresses), its bottom being pointed by SS:SP. There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return address.

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