WDC 65C265

WDC 65C265

The Western Design Center (WDC) W65C265S microcomputer is a complete fully static 16-bit computer fabricated on a single chip using a Hi-Rel low power CMOS process. The W65C265S complements an established and growing line of 65xx products and has a wide range of microcomputer applications. The W65C265S has been developed for Hi-Rel applications and where minimum power is required.

The W65C265S consists of a W65C816S (Static) Central Processing Unit (CPU), 8 kB of Read Only Memory (ROM), 576 bytes of Random Access Memory (RAM), Processor defined cache under software control, eight 16-bit timers with maskable interrupts, high performance interrupt-driven Parallel Interface Bus (PIB), four Universal Asynchronous Receivers and Transmitters (UART) with baud rate timers, Monitor "Watch Dog" Timer with "restart" interrupt, twenty-nine priority encoded interrupts, Built-in Emulation features, Time of Day (ToD) clock features, Twin Tone Generators (TGx), Bus Control Register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features.

The innovative architecture and demonstrated high performance of the W65C265S CPU, as well as instruction simplicity, result in system cost-effectiveness and a wide range of computational power. These features make the W65C265S a leading candidate for 16-bit microcomputer applications especially where task oriented processing is desired.

This product description assumes that the reader is familiar with the W65C816S CPU hardware and programming capabilities. Refer to the W65C816S Data Sheet for additional information.