History
SystemVerilog started with the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009, the current version.
The feature-set of SystemVerilog can be divided into two distinct roles:
- SystemVerilog for RTL design is an extension of Verilog-2005; all features of that language are available in SystemVerilog.
- SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog.
The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005.
Read more about this topic: System Verilog
Famous quotes containing the word history:
“Free from public debt, at peace with all the world, and with no complicated interests to consult in our intercourse with foreign powers, the present may be hailed as the epoch in our history the most favorable for the settlement of those principles in our domestic policy which shall be best calculated to give stability to our Republic and secure the blessings of freedom to our citizens.”
—Andrew Jackson (1767–1845)
“Only the history of free peoples is worth our attention; the history of men under a despotism is merely a collection of anecdotes.”
—Sébastien-Roch Nicolas De Chamfort (1741–1794)
“Perhaps universal history is the history of the diverse intonation of some metaphors.”
—Jorge Luis Borges (1899–1986)