System Verilog - History

History

SystemVerilog started with the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009, the current version.

The feature-set of SystemVerilog can be divided into two distinct roles:

  1. SystemVerilog for RTL design is an extension of Verilog-2005; all features of that language are available in SystemVerilog.
  2. SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog.

The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005.

Read more about this topic:  System Verilog

Famous quotes containing the word history:

    In the history of the United States, there is no continuity at all. You can cut through it anywhere and nothing on this side of the cut has anything to do with anything on the other side.
    Henry Brooks Adams (1838–1918)

    The steps toward the emancipation of women are first intellectual, then industrial, lastly legal and political. Great strides in the first two of these stages already have been made of millions of women who do not yet perceive that it is surely carrying them towards the last.
    Ellen Battelle Dietrick, U.S. suffragist. As quoted in History of Woman Suffrage, vol. 4, ch. 13, by Susan B. Anthony and Ida Husted Harper (1902)

    The history of the world is none other than the progress of the consciousness of freedom.
    Georg Wilhelm Friedrich Hegel (1770–1831)