History
SystemVerilog started with the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009, the current version.
The feature-set of SystemVerilog can be divided into two distinct roles:
- SystemVerilog for RTL design is an extension of Verilog-2005; all features of that language are available in SystemVerilog.
- SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog.
The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005.
Read more about this topic: System Verilog
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