History of The Specifications
These agreements grew out of the POS-PHY interface definitions PL-3 and PL-4 which themselves came from the ATM Forum's Utopia definitions which had included:
- Utopia Level 1, an 8 bit, 25 MHz interface supporting OC-3 and slower links (or multiple links aggregating to less than 200 Mbit/s).
- Utopia Level 2, a 16 bit, 50 MHz interface supporting OC-12 or multiple links aggregating to less than 800 Mbit/s.
System Packet Interface or SPI as it is widely known is a protocol for packet and cell transfers between PHY and LINK layer devices in multi-gigabit applications. This protocol has been developed by Optical Internetworking Forum (OIF) and is fast emerging as one of the most important integration standards in the history of telecommunications and data networking. Devices implementing SPI are typically specified with line rates of 700~800 Mbit/s and in some cases up to 1 Gbit/s. The latest version is SPI 4 Phase 2 also known as SPI 4.2 delivers bandwidth of up to 16 Gbit/s for a 16 bit interface.
Read more about this topic: System Packet Interface
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