Sum Addressed Decoder - Ignoring The LSBs: Late Select On Carry

Ignoring The LSBs: Late Select On Carry

The formulation above checks the entire result of an add. However, in a CPU cache decoder, the entire result of the add is a byte address, and the cache is usually indexed with a larger address, in our example, that of an 8-byte block. It is preferable to ignore a few of the LSBs of the address. However, the LSBs of the two addends can't be ignored because they may produce a carry-out which would change the doubleword addressed.

If R and O are added to get some index I, then the actual address Addr is equal to either I, or I + 1, depending on whether R+O generates a carry-out. Both I and I+1 can be fetched if there are two banks of SRAM, one with even addresses and one with odd. The even bank holds addresses 000xxx, 010xxx, 100xxx, 110xxx, etc., and the odd bank holds addresses 001xxx, 011xxx, 101xxx, 111xxx, etc. The carry-out from R+O can then be used to select the even or odd doubleword fetched later.

Note that fetching from two half-size banks of SRAM will dissipate more power than fetching from one full-size bank, since we are switching more sense amps and data steering logic.