P2SC
The P2SC, for POWER2 Super Chip, was released in October 1996 as the successor of the POWER2. It was a single-chip implementation of the eight-chip POWER2, integrating 15 million transistors on a 335 mm2 die manufactured in IBM's 0.29 μm five-layer metal CMOS-6S process. The first version ran at 120 or 135 MHz, nearly twice as fast as the POWER2 at 71.5 MHz, with the memory and I/O buses running at half speed to support the higher clock frequency. IBM claimed that the performance of this version was 5.5 SPECint95_base and 14.5 SPECfp95_base. A faster 160 MHz part fabricated in the 0.25 μm CMOS-6S2 process was announced at the Microprocessor Forum in October 1997.
The P2SC was not a complete copy of the POWER2, the L1 data cache and data translation lookaside buffer (TLB) capacities were halved to 128 KB and 256 entries, respectively, and a rarely used feature that locked entries in the TLB was not implemented in order to fit the original design onto a single die.
The P2SC was succeeded by the POWER3 as IBM's flagship microprocessor on the RS/6000 line in 1998. A notable use of the P2SC was the 30-node IBM Deep Blue supercomputer that beat world champion Garry Kasparov at chess in 1997. However, the computer's chess-playing capabilities were due to its custom integrated circuits, rather than the P2SCs.
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