P6 Variant Enhanced Pentium M (microarchitecture)
| L1 cache | 64 KB |
|---|---|
| L2 cache | 1 MB to 2 MB 2 MB (Xeon) |
| Predecessor | Pentium M |
| Successor | Intel Core |
The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the foregoing Pentium M's shortcomings, by adding to its P6 microarchitecture:
- SSE3 Support
- Single- and dual-core technology with 2 MB of shared L2 cache (restructuring processor organization)
- Increased FSB speed, with the FSB running at 533 MT/s or 667 MT/s.
- A 12-stage instruction pipeline.
This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.
Read more about this topic: P6 (microarchitecture)
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