P6 (microarchitecture) - From Pentium Pro To Pentium III

From Pentium Pro To Pentium III

The P6 core was the sixth generation Intel microprocessor in the x86 line. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).

Some techniques first used in the x86 space in the P6 core include:

• Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs.
• Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M.
• PAE and wider 36-bit address bus to support 64 GB of physical memory (the linear address space of a process was still limited to 4 GB).
• Register renaming, which enabled more efficient execution of multiple instructions in the pipeline.
• CMOV instructions heavily used in compiler optimization.

The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). The P6 line of processing cores was succeded with the NetBurst (P68) architecture which appeared with the introduction of Pentium 4. This was a completely different design based on the use of very long pipelines that favoured high clock speed at the cost of lower IPC, and higher power consumption.