NOP Machine Instruction
Some computer instruction sets include an instruction whose explicit purpose is not to change the state of any of the programmer accessible registers, status flags, or memory and which may require a specific number of clock cycles to execute. In other instruction sets, a NOP has to be simulated by executing an instruction having operands that cause the same effect (e.g., on the SPARC processor, the instruction sethi 0, %g0 is the recommended solution).
A NOP is most commonly used for timing purposes, to force memory alignment, to prevent hazards, to occupy a branch delay slot, or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when refactoring would be problematic or time-consuming). In some cases, a NOP can have minor side effects; for example, on the Motorola 68000 series of processors, the NOP opcode causes a synchronization of the pipeline.
Here are the characteristics of the NOP instruction for some CPU architectures:
| CPU architecture | Mnemonic | Bytes | Opcode | Notes |
|---|---|---|---|---|
| Intel x86 CPU family | NOP |
1; 1–9 for i686 | 0x90; 0x0f 0x1f | The NOP instruction on the x86 CPU family is actually XCHG EAX, EAX (resulting the same opcode 0x90) - an instruction without any effect. |
| Intel 8051 / MCS-51 family | NOP |
1 | 0x00 | |
| ARM | NOP |
4 | 0x00000000 | This stands for andeq r0, r0, r0 which has no effect. The assembly instruction nop will most likely expand to mov r0, r0 which is encoded 0xE1A00000. |
| Thumb-2 (16 bit) | NOP |
2 | 0xbf00 | |
| Thumb-2 (32 bit) | NOP |
4 | 0xf3af 1000 | |
| MIPS | NOP |
4 | 0x00000000 | Stands for sll r0,r0,0 |
| MIPS-X | NOP |
4 | 0x60000019 | (extended opcode for add r0,r0,r0) |
| MMIX | SWYM |
4 | 0xfd****** | SWYM stands for “Sympathize with your machinery.” The * digits can be chosen arbitrarily. |
| Motorola 68000 family | NOP |
2 | 0x4e71 | This synchronizes the pipeline and prevents instruction overlap. |
| MOS Technology 65xx | NOP |
1 | 0xea | NOP consumes two clock cycles. Undefined opcodes in the NMOS versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the 65C02. |
| PowerPC | NOP |
4 | 0x60000000 | (extended opcode for ori r0,r0,0) |
| PIC microcontroller | NOP |
12 bits | 0b000000000000 | |
| SPARC | NOP |
4 | 0x01000000 | |
| Z80 | NOP |
1 | 0x00 |
From a hardware design point of view, unmapped areas of a bus are often designed to return zeroes; since the NOP slide behavior is often desirable, it gives a bias to coding it with the all-zeroes opcode.
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