Multiple Patterning - Multiple Patterning - The Ultimate Resolution

The Ultimate Resolution

The extrapolation of double patterning to multiple patterning has been contemplated, but the issue of cost control is still on the minds of many. While the benefits of multiple patterning in terms of resolution, depth of focus and lithographic defect sensitivity are understood, there is added burden to control the process budget increase and maintain good yield.

Beyond double (2X) patterning, the most frequently published multiple patterning methodology is the repeated spacer approach, which can be practiced in many forms. A multilayer-on-topography spacer-type approach also offers some flexibility. It is also possible to additively combine two or more of the above approaches. For example, a dual-tone photoresist with pitch-halved acid profile, plus dual-tone development that dissolves the highest and lowest acid concentrations, combined with a spacer process, would result in 8x pitch resolution enhancement,e.g., 40 nm half-pitch reduced to 5 nm half-pitch. Subsequently repeating the spacer process would give 16 x pitch resolution improvement, e.g., 40 nm half-pitch reduced to 2.5 nm half-pitch. The European LENS (Lithography Enhancement Towards Nano Scale) project is targeted toward implementation of both double exposure (resist freezing) and spacer-based process, in principle enabling two ways of patterning for ~20 nm design rules with current lithography tools, already tailored for double patterning or ~10 nm design rules in combination. With successful dual-tone development of a dual-tone photoresist, 2.5 nm design rules can be imagined.

Intel used several spacer deposition/etch/clean steps to demonstrate spacers spaced apart by ~26 nm. It represents a reduction of the original patterned pitch by a factor of ~1/4 and indicates that wavelength and optics no longer purely determine the lithographic resolution.

IMEC has indicated that in the event that EUV lithography is not ready, quadruple patterning (with tighter overlay specifications) would be used.

At the 2010 Flash Memory Summit, it was projected that immersion lithography with multiple patterning would be used to scale NAND Flash to below 20 nm within a few years.