Multiple Patterning - Implementations

Implementations

Due to its rather straightforward application, without the need to change the infrastructure, multiple patterning is not expected to encounter any insurmountable technical or commercialization barriers. Despite the cost and throughput concerns, it has recently received more attention and interest, mainly due to delays in next-generation lithography techniques such as EUVL and nanoimprint lithography.

Multiple patterning can also exploit high-bias processes (for example, photoresist trimming to reduce linewidth, or photoresist reflow to reduce trench width) to substantially eliminate defects sized at around 2x the design pitch or smaller. This is a significant advantage over increasing lithography tool resolution, which exposes the wafer to more defects at the design rule or even smaller.