How DRAM Refresh Works
While the memory is operating, each memory cell must be refreshed repetitively, within the maximum interval between refreshes specified by the manufacturer, which is usually in the millisecond region. Refreshing does not employ the normal memory operations (read and write cycles) used to access data, but specialized cycles called refresh cycles which are generated by separate counter circuits in the memory circuitry and interspersed between normal memory accesses.
The storage cells on a memory chip are laid out in a rectangular array of rows and columns. The read process in DRAM is destructive and removes the charge on the memory cells in an entire row, so during a normal read operation the sense amplifiers on the chip, after reading and latching the data, rewrite the data in the accessed row before sending the bit from a single column to output. So the read electronics has the ability to refresh an entire row of memory in parallel, significantly speeding up the refresh process. A normal read or write cycle refreshes a row of memory, but normal memory accesses cannot be relied on to hit all the rows within the necessary time, so an abbreviated cycle called a refresh cycle is used. The refresh cycle is identical internally to a read cycle, except that it produces no data. The only difference between a read and a refresh cycle is:
- Only the row address is needed, so a column address doesn't have to be applied to the chip address circuits.
- Data read from the cells is not latched into the output buffers and put on the data bus.
The refresh circuitry must perform a refresh cycle on each of the rows on the chip within the refresh time interval, to make sure that each cell gets refreshed.
Read more about this topic: Memory Refresh
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