Memory Refresh - Comparison of Static and Dynamic RAM

Comparison of Static and Dynamic RAM

In static random access memory (SRAM), the other type of semiconductor memory, the data is not stored as charge on a capacitor but in a pair of transistors called a flip-flop, so SRAM does not require refreshing. The two basic types of memory have advantages and disadvantages. Static memory can be considered permanent while powered on, i.e. once written the memory stays until specifically changed and thus its use tends to be simple in terms of system design. However the internal construction of each static memory cell requires six transistors, compared to the single transistor required for a dynamic RAM cell, so the density of SRAM is much lower and price-per-bit much higher than DRAM. The complexity of the static memory cell is also relatively slow to operate thus static memory tends to have lower bandwidths than equivalent dynamic storage. Writing the capacitor of the dynamic cell is very rapid and write-access times on modern dynamic storage can be in single digit nano-seconds.

Modern DRAM modules provide the refresh circuitry on-board with no requirement for motherboard circuitry, almost to the point where, at a module level, they may be thought of as static - requiring the CPU to do nothing to preserve their content. Some CPUs (e.g. the Zilog Z80) provided special internal registers that could provide the Row-Address Strobe (RAS) to refresh dynamic memory cells, the register being incremented on each refresh cycle. The availability of a RAS refresh was signalled by a unique combination of address and control wires during operationally redundant clock cycles (T-States), i.e. during instruction decode/execution when the buses may not be required. Instead of the bus being inactive during such t-states, the refresh register would be presented on the address bus along with a combination of control wires to indicate to the refresh circuitry. In early versions of the Z80 a lack of fore-sight resulted in the R register being only 7 bits long. With the rapid advent of 64Kbit+ DRAM chips (with an 8 bit RAS), extra circuitry had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory being lost after a few milli-seconds. Usually in the form of an 8-bit counter chip, the output was used to provide the refresh RAS address instead of the R register. The refresh signal from the CPU was used as the clock for this counter resulting in the memory row to be refreshed being incremented with each refresh cycle. Later versions and licensed "work-alikes" of the Z80 core remedied the missing 8th bit and modern CPUs have greatly expanded on such basic provisioning to provide rich all-in-one solutions for DRAM refresh.