Memory Divider - Example

Example

Suppose a computer system has DDR memory, a Memory Divider of 1:1, a FSB operating at 200 MHz and a CPU multiplier of 10x. Then, the base memory clock will operate at (Memory Divider) × (FSB) = 1 × 200 = 200 MHz and the effective memory clock would be 400 MHz since it's a DDR system ("DDR" stands for Double Data Rate; the effective memory clock speed is double the actual clock speed). The CPU will operate at 10 × 200 MHz = 2.0 GHz. Using I/O bus frequency of 200 MHz various types of DRAM will operate as:

DDR SDRAM at 400 MHz (DDR-400 or PC-3200) DDR2 SDRAM at 800 MHz (DDR2-800 or PC2-6400) DDR3 SDRAM at 1600 MHz (DDR3-1600 or PC3-12800)

Now suppose that we overclock FSB to 250 MHz so that CPU operates at 10 × 250 MHz = 2.5 GHz and memory clock operates at 250 MHz (Memory Divider × FSB). Since DDR-400 RAM is used then effective memory clock (Actual Memory Frequency) will be 500 MHz. A normal DDR-400 SDRAM will fail to work at 500 MHz since it is designed to work at 400 MHz and system will become unstable. But a modern CPU (having overclocking potential) can work at 2.5 GHz (even if it is designed to work at 2 GHz) flawlessly without giving any problem of stability. To keep running overclocked CPU at 2.5 GHz or even at higher speeds (by increasing FSB) we need to slow down memory clock so as to achieve a stable system. For this if we decrease DRAM:FSB ratio to say 4:5 then resulting memory clock speed is (4/5) × 250 MHz = 200 MHz resulting effective clock speed of 400 MHz on DDR-400. So, we are able to operate upon a stable overclocked CPU at 2.5 GHz from 2 GHz without increasing effective memory clock.