Machine Check Architecture

In computing, Machine Check Architecture (MCA) refers to a mechanism in which the CPU reports hardware errors to the operating system.

Intel's Pentium 4, Intel Xeon, P6 family processors as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.

A similar concept in IBM servers is referred to as first failure data capture.

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    Samuel Taylor Coleridge (1772–1834)