Itanium - Architecture

Architecture

"IA-64" redirects here. For AMD64 and Intel64 architecture, see x86-64.
Intel Itanium Architecture
Designer HP and Intel
Bits 64
Introduced 2001
Design EPIC
Type Register-Register
Endianness Selectable
Registers
  • 128 64-bit general purpose registers
  • 128 82-bit floating-point registers
  • 64 1-bit predicate registers

Intel has extensively documented the Itanium instruction set and microarchitecture, and the technical press has provided overviews. The architecture has been renamed several times during its history. HP originally called it PA-WideWord. Intel later called it IA-64, then Itanium Processor Architecture (IPA), before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64.

It is a 64-bit register-rich explicitly parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 264 bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.

The architecture implements 128 integer registers, 128 floating point registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.

Read more about this topic:  Itanium

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