Instruction Set Architecture Family
The EISC has 16-bit, 32-bit and 64-bit instruction set architecture family. There exist SE(simple EISC) series and AE(Advanced EISC) series.
- SE1608: 16-bit simple EISC family. 3-operand instruction set architecture. Not a compressed code architecture but it also uses LERI instruction to fully support 16-bit immediate value diretly.
- SE3208: 32-bit simple EISC family. 3-operand instruction set architecture. 8 GPRs.
- AE32000: 32-bit Advanced EISC family for embedded microprocessing market. 2-operand instruction set architecture. 16 GPRs. It also has SIMD-DSP capability. The Newest instruction set architecture is AE32000C (AE32000-revision C)
- AE64000: 64-bit Advanced EISC family for embedded microprocessing market especially robot and multimedia market.
| Class | Core | Process | Clock Freq. | Average IPC | Peak MIPS | Gate Counts | Power Consumption(@0.18 μm) | Pipelines | SIMD-DSP |
|---|---|---|---|---|---|---|---|---|---|
| SE | SE1608 | 16-bit CPU | 70 MHz@0.18 μm | 8K | 3 stages | ||||
| SE3208 | 32-bit CPU | 70 MHz@0.18 μm | 13K | 3 stages | |||||
| AE | AE32000C-Tiny | up to 100 MHz@0.18 μm | over 0.8 | 110 MIPS@100 MHz | 26~30K | under 0.15 mW/MHz | 3 stages | ||
| AE32000C-Lucida | up to 150 MHz@0.18 μm | over 0.87 | 145 MIPS@130 MHz | 50~88K | under 0.30 mW/MHz | 5 stages | SIMD-DSP | ||
| AE32000C-Empress | up to 300 MHz@0.13 μm | over 0.78 | 120K | under 0.38 mW/MHz | 9 stages | SIMD-DSP |
Read more about this topic: Extendable Instruction Set Computer
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