Digital Delay Generator - DDG Design

DDG Design

A key issue in the design of DDGs is to generate triggered delays having crystal-oscillator precision but that are not quantized to the edges of the reference oscillator. There are a number of techniques used in digital delay generation.

• The simplest scheme simply uses a digital counter and a free-running crystal oscillator to time intervals with 1-clock ambiguity, resulting in output edge jitter of one clock period peak-to-peak relative to an asynchronous trigger. This technique is used in the Quantum Composers and Berkeley Nucleonics instruments.

• Triggered crystal, LC, or delay-line oscillators may be started at trigger time, and subsequently counted to make coarse delays, followed by an analog fine or "vernier" delay to interpolate between clock periods. An enhancement is to use a phase-locked loop to lock the startable oscillator to a more accurate continuous-running crystal oscillator using a technique that preserves the original trigger alignment. The classic Hewlett Packard 5359A Time Synthesizer used a triggered ECL delay-line oscillator which was synchronized to a crystal oscillator using a heterodyne phaselock technique; the technique was subsequently used in several Berkeley Nucleonics and LeCroy delay generators. Highland Technology uses a triggered LC oscillator and a DSP phaselock scheme. Jitter below 10 ps RMS relative to an external trigger can be achieved.

• It is possible to design an analog-ramp delay generator, using a current source to charge a capacitor, that spans some tens of nanoseconds of delay range. One can then suspend the ramp current for some integral number of clocks, as timed by a crystal oscillator. The freezing of the ramp extends the range of delays without the requirement to synchronize the oscillator to the trigger. This technique is described in US patent 4,968,907 and was used in the Signal Recovery instrument. Low delay jitter is possible, but leakage current becomes a serious error contributor for delays in the millisecond range.

• A flipflop-based dual-rank synchronizer can be used to synchronize an external trigger to a counter-based delay generator, as in case (1) above. It is then possible to measure the skew between the input trigger and the local clock and adjust the vernier delay, on a shot-by-shot basis, to compensate for most of the trigger. Jitter in the tens of picoseconds RMS can be achieved with careful calibration. This technique is used by Stanford Research Systems.